- Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed crypto applications.
- S/he will architect, implement high speed crypto architectures, on ASICs / Xilinx Zynq/MPSOC class FPGAs.
- S/he will be responsible for deriving engineering specifications from system requirements, detailed architecture, design (RTL, HLS (C++ to RTL)) and RTL quality (CDC, Formal, Lint), Test plans, module level verification, synthesis/STA, Lab debug, SW driven validation on Linux based SOC evaluation boards, Silicon/FPGA bring up, characterization and production ramp/support/collateral.
- Our company has state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA with HLS, Mentor EDA Family: Questa, VIPs, UVM framework: Clock Domain Crossing (CDC), Catapult (HLS).
- This is a key, high impact role in the organization to ensure robust quality and delivery of Communication products for National Security.
- Architecting, implementing high throughput digital cores / algorithms targeting Xilinx Zynq / MPSOC class FPGAs with interfaces Ethernet (UDP, TCP/IP), AXI, PCIe/NVMe, USB.
- RTL design (VHDL) design, debug.
- C/C++ modelling/design
- Proficient with CDC, Formal flows. Preference for Mentor EDA.
- Proficient in VHDL, C++ (OOP), Perl/Tcl
- Proficient with Synthesis/PAR: SDC, Synopsys DC/Synplify, Vivado, Quartus
- Bachelor's Degree in Electrical or other engineering discipline and 6+ years of experience developing, implementing, and verification of high-performance communications/network ASIC/FPGA products
- Master's Degree preferred.
- MUST EITHER HAVE A SECRET CLEARANCE OR BE ABLE TO OBTAIN ONE
Preferred Additional Skills:
- Proficiency in High level synthesis (Xilinx Vivado HLS AND/OR Mentor Calypto) with C++.
- Proficiency with Xilinx MPSOC design with writing/debugging with SDKs, BSPs on bare metal/PetaLinux OS.
- Linux Super User
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